A Design Technique for Polyphase Decimators with Binary Constrained Coefficients for High Resolution A/D Converters

This paper presents a design technique for high fidelity multistage decimation filters based on the polyphase and decimator structures presented in [1][2], catering for powers of two sample-rate decreases. The technique is well suited for Analog-to-Digital Converter (ADC) applications in excess of 16 bit resolution. The resulting filter coefficients are constrained to the required bit length using a "bit flipping algorithm" [3]. This technique is comparatively presented through an example of a cascaded decimation filter, designed for a 20-bit resolution ADC and compared to with other approximation methods. The coefficients and frequency responses of the cascaded filter are reported.